Publications

Publications

Reviewed Journal

2006

• J. Uchida, N. Togawa, M. Yanagisawa, and T. Ohtsuki, "A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier," IEICE Trans. Electron., Vol.E89-C, No.3, pp243-249, Mar. 2006.

2005

• N. Togawa, H. Kawazu, J. Uchida Y. Miyaoka, M. Yanagisawa, and T. Ohtsuki, "Sub-operation Parallelism Optimization in SIMD Processor Synthesis and Its Experimental Evaluations," IEICE Trans. Fundamentals, Vol.E88-A, No.4, pp.876-884, Apr. 2005.
• N. Togawa, K. Tachikake, Y. Miyaoka, M. Yanagisawa, and T. Ohtsuki, "A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition," IEICE Trans. Inf. & Syst., Vol.E88-D, No.7, pp.1340-1349, Jul. 2005.

2004

• Y. Miyaoka, N. Togawa, M. yanagisawa, and T. Ohtsuki, "A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths," IEICE Trans. Fundamentals, Vol.E87-A, No.4, pp.830-836, Apr. 2004.
• K. Shimizu, J. Uchida, N. Togawa, M. Yanagisawa, and T. Ohtsuki, "FPGA-Based Reconfigurable Adaptive FEC," IEICE Trans. Fundamentals, Vol.E87-A, No.12, pp.3036-3046, Dec. 2004.
• J. Uchida, N. Togawa, M. Yanagisawa, and T. Ohtsuki, "High-Level Power Optimization Based on thread Partitioning," IEICE Trans. Fundamentals, Vol.E87-A, No.12, pp.3075-3082, Dec. 2004.
• Y. Shi, S. Kimura, M. Yanagisawa, and T. Ohtsuki, "A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs," IEICE Trans. Fundamentals, Vol.E87-A, No.12, pp.3193-3199, Dec. 2004.
• Y. Shi, S. Kimura, M. Yanagisawa, and T. Ohtsuki, "A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction," IEICE Trans. Fundamentals, Vol.E87-A, No.12, pp.3208-3215 , Dec. 2004.

2003

• N. Togawa, Takao Totsuka, T. Wakui, M. Yanagisawa, and T. Ohtsuki, "A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories," IEICE Trans. Fundamentals, Vol.E86-A, No.5, pp.1082-1092, May 2003.
• Y. Shi, Zhe Zhang, S. Kimura, M. Yanagisawa, and T. Ohtsuki, "A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation," IEICE Trans. Fundamentals, Vol.E86-A, No.12, pp.3056-3062, Dec. 2003.
• N. Togawa, K. Tachikake, Y. Miyaoka, M. Yanagisawa, and T. Ohtsuki, "A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions," IEICE Trans. Fundamentals, Vol.E86-A, No.12, pp.3218-3224, Dec. 2003.

2002

• S. Noda, N. Togawa, M. Yanagisawa, and T. Ohtsuki, "High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks," IEICE Trans. Fundamentals, Vol.E85-A, No.4, pp.827-834, Apr. 2002.
• J. Choi, N. Togawa, M. Yanagisawa, and T. Ohtsuki, "An algorithm and a flexible architecture for fast block-matching motion estimation," IEICE Trans. Fundamentals, Vol.E85-A, No.12, pp.2603-2611, Dec. 2002.
• S. Noda, N. Togawa, M. Yanagisawa, and T. Ohtsuki, "A high-level energy-optimizing algorithm for system VLSIs with Gated Clocks," IEICE Trans. Fundamentals, Vol.E85-A, No12, pp.2655-2666, Dec. 2002.

2001

• N. Togawa, M. Ienaga, M. Yanagisawa, and T. Ohtsuki, "An Area/Time Optimizing Algorithm in High-Level Synthesis of Control-Based Hardwares," IEICE Trans. Fundamentals, Vol.E84-A, No. 5, pp.1166-1176, May 2001.
• N. Togawa, Y. Kataoka, Y. Miyaoka, M. Yanagisawa, and T. Ohtsuki, "Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores," IEICE Trans. Fundamentals, Vol.E84-A, No. 11, pp.2639-2647, Nov. 2001.
• N. Togawa, T. Sakurai, M. Yanagisawa, and T. Ohtsuki, "A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files," IEICE Trans. Fundamentals, Vol.E84-A, No. 11, pp.2802-2807, Nov. 2001.

2000

• N. Togawa, M. Yanagisawa, and T. Ohtsuki, "A Hardware/Software Cosynthesis for Digital Signal Processor Cores with Two Types of Register Files," IEICE Trans. Fundamentals, Vol.E83-A, No.3, pp.442-451, Mar. 2000.
• Z. Zing-Rong, M. Yanagisawa, and T. Ohtsuki," A High Performance Embedded Wavelet Video Coder," IEICE Trans. Fundamentals, Vol.E83-A, No.6, pp.979-986, Jun. 2000.
• N. Togawa, T. Wakui, T. Yoden, Makoto Terajima, M. Yanagisawa, and T. Ohtsuki, "CAM Processor Synthesis Based on Behavioral Descriptions," IEICE Trans. Fundamentals, Vol.E83-A, No.12, pp.2464-2473, Dec. 2000.

1999

• N. Togawa, K. Ara, M. Yanagisawa, and T. Ohtsuki, "A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs," IEICE Trans. Fundamentals, Vol.E82-A, No.3, pp.473-482, Mar. 1999.
• Z. Zing-Rong, M. Yanagisawa, and T. Ohtsuki, "Fast Motion Esitimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlation," Journal of Circuits, and Computers, Vol.9, Nos.1 & 2, pp.67-82, Sep. 1999.
• N. Togawa, Kaoru Ukai, M. Yanagisawa, and T. Ohtsuki, "A simultaneous placement and global routing alogorithm for FPGAs with power optimization," Journal of Circuits, and Computers, Vol.9, Nos.1 & 2, pp.99-112, Sep. 1999.
• N. Togawa, M. Yanagisawa, and T. Ohtsuki, "A Hardware/Software Cosynthesis for Digital Signal Processor Cores," IEICE Trans. Fundamentals, Vol.E82-A, No. 11, pp.2325-2337, Nov. 1999.

1998

• N. Togawa, K. Hagi, M. Yanagisawa, and T. Ohtsuki, "An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications," IEICE Trans. Fundamentals, Vol.E81-A, No.5, pp.873-884, May 1998.
• N. Togawa, M. Yanagisawa, and T. Ohtsuki, "A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis," IEICE Trans. Fundamentals, Vol.E81-A, No.6, pp.1231-1241, Jun. 1998.
• N. Togawa, M. Yanagisawa, and T. Ohtsuki, "Maple-opt: A Performance-Oriented Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGA's," IEEE Trans. CAD of IC and Systems, Vol.17, No.9, pp.803-818, Sep. 1998.
• N. Togawa, T. Hisaki, M. Yanagisawa, and T. Ohtsuki, "A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration," IEICE Trans. Fundamentals, Vol.E81-A, No.12, pp.2563-2575, Dec. 1998.

1997

• N. Togawa, M. Sato, and T. Ohtsuki, "A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems," IEICE Trans. Fundamentals, Vol.E80-A, No.3, pp.494-505, Mar. 1997.
• N. Togawa, M. Sato, and T. Ohtsuki, "A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs," IEICE Trans. Fundamentals, Vol.E80-A, No.10, pp.1795-1806, Oct. 1997.
• K. Suzuki, N. Togawa, M. Sato, and T. Ohtsuki, "Fast Scheduling and Allocation Algorithms for Entropy CODEC," IEICE Trans. Information and Systems, Vol.E80-D, No.10, pp.982-992, Oct. 1997.

1996

• N. Togawa, M. Sato, and T. Ohtsuki, "A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints," IEICE Trans. Fundamentals, Vol.E79-A, No.3, pp.321-329, Mar. 1996.
• N. Togawa, M. Sato, and T. Ohtsuki, "Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout," IEICE Trans. Fundamentals, Vol.E79-A, No.12, pp.2140-2150, Dec. 1996.

1995

• S. Ohno, M. Sato, and T. Ohtsuki, "A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size," IEICE Trans. Fundamentals, Vol.E78-A, No.12, pp.1755-1764, Dec. 1995.
• N. Togawa, M. Sato, and T. Ohtsuki, "A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems," IEICE Trans. Fundamentals, Vol.E78-A, No.12, pp.1765-1776, Dec. 1995.

1994

• N. Togawa, M. Sato, and T. Ohtsuki, "Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays," IEICE Trans. Fundamentals, Vol.E77-A, No.12, pp.2028-2038, Dec. 1994.

1993

• M. Sato, "A Computer Network Characterization in terms of Partial k-trees," Memoirs of the College of Science and Engineering, Waseda University, No.56, pp.75-86, Mar. 1993.
• T. Awashima, M. Sato, and T. Ohtsuki, "Optimal Constraint Graph Generation Algorithm for Layout Compaction Using Enhanced Plane-Sweep Method," IEICE Trans. Fundamentals, Vol.E76-A, No.4, pp.507-512, Apr. 1993.

1992

1991

• T. Takizawa, K. Kubota, M. Sato, and T. Ohtsuki, "A VLSI Geometrical Design Rule Verification Accelerated by CAM-Based Hardware Engine," IEICE Trans. Fundamentals, Vol.E74, No.10, pp.3072-3077, Oct. 1991.